Dynamic Random Access Memory with Self-controllable Voltage Level to reduce low leakage current in VLSI

Today trend is circuit characterized by reliability, low power dissipation, low leakage current, low cost and there is required to reduce each of these. To reduce device size and increasing chip density have increase the design complexity. The memories have provided the system designer with components of considerable capability and extensive application. Dynamic random access memory (DRAM) gives the advantage for highdensity data storage. DRAM basically a memory array with individual bit access refers to memory with both Read and Write capabilities. Here 3T DRAM is implementing with self controllable voltage level (svl) technique is for reducing leakage current in 0.12um technology. The simulation is done by using microwind 3.1 & dsch2 and gives the advantage of reducing the leakage current up to 57%.